The present application relates generally to semiconductor devices, and more specifically to vertical field effect transistors with self-aligned gate and source/drain (S/D) contacts.
Vertical field effect transistors (VFETs) are fin-based nonplanar transistors in which current flows from a bottom S/D region to a top S/D region through a fin-shaped channel region in a direction that is normal to a substrate surface. VFETs employ side-gates that wrap around sidewalls of the fin-shaped channel and can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. An advantage of a VFET is its decreased footprint, which may beneficially impact device scaling relative to alternate geometries. A VFET can achieve a smaller device footprint because its channel length is decoupled from the contacted gate pitch.